1. Field of the Invention
The present invention relates generally to a semiconductor memory device. More specifically, the invention relates to a dynamic semiconductor memory device (DRAM) required to rewrite read data.
2. Related Background Art
A memory cell array of a DRAM is formed by providing bit lines and word lines, which intersect each other, and by arranging dynamic memory cells, each of which has one transistor/one capacitor, at the respective intersections. Each of the bit lines of the memory array is provided with a bit line sense amplifier. By selectively driving the word lines, data of a plurality of memory cells are read out to a plurality of corresponding bit lines. These bit line data are selected by a column selecting gate to be transferred to a corresponding data line. The data transferred to the data line are detected and amplified by a corresponding one of data line sense amplifiers to be outputted.
Thus, in the data readout operation for the DRAM, the bit line data are detected and amplified by the corresponding one of the bit line sense amplifiers having a small drive capacity. Therefore, after the potential amplitude of the bit lines increases to such an extent that data destruction does not occur, the column selecting gate is open, so that the bit line data are transmitted to the data line (step (a)). Because, if not so, there is the possibility that data destruction occurs due to charge distribution caused by connecting the bit lines to the corresponding data line. After the bit line data are transferred to the data line, the data line is separated from the corresponding one of the data line sense amplifiers, and the transferred data are amplified to a full amplification level to be outputted (step (b)). The reason why the data line is separated is that a data line capacity is separated from the corresponding one of the data line sense amplifiers to carry out rapid detection and amplification.
In the above described typical data readout method for DRAMs, there is a problem in order to further promote the capacity increase, scale down and accelerating of DRAMs. That is, with the capacity increase and scale down of DRAMs, a large number of memory cells are connected to bit lines, so that the bit line capacity increases. On the other hand, with the scale down, the drive capacity of the bit line sense amplifier, which must be arranged in a bit line pitch, relatively decreases. Therefore, it takes a lot of time to amplify data read out to the bit lines, to some extent of amplitude. This obstructs rapid readout.
Conventionally, as rapid data readout techniques for DRAMs, there are proposed (1) a system for providing a read-only sense amplifier and a restore-only sense amplifier in a bit line (Japanese Patent Laid-Open No. 8-147975), and (2) a system for providing a global bit line shared by a plurality of bit lines in a memory array, providing a pre-sense amplifier in each of the bit lines, and providing a restoring sense amplifier in the global bit line (Japanese Patent Laid-Open No. 5-144253).
However, in these systems, although the sense amplifiers are divided every function, all of the sense amplifiers must be arranged in a bit line pitch in a memory cell array region on a layout. As described above, in the memory array region, the bit line pitch is very small by the scale down technique, so that there is a limit to the drive capacity of the sense amplifier arranged in the memory cell array region.